1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device equipped with a test function and a method of setting a test mode in a semiconductor device.
2. Description of the Related Art
Semiconductor device manufacturers need to test the manufactured semiconductor devices prior to shipment from the factory in order to check whether they operate properly. Semiconductor devices are provided not only with a normal operation mode for exerting the functions that are originally intended for these semiconductor devices, but also with a test mode for performing special functions for test purposes. At the test prior to shipment from the factory, semiconductor devices are controlled to enter such a test mode so as to perform test operations that are different from the normal operations. This serves to check the semiconductor devices.
In the case of a microcontroller implemented as a single chip including a CPU, ROM, RAM, and so on, there is a need to lead some signals to an exterior of the chip for inspection in the test mode while these signals are only transmitted between internal modules such as the CPU, ROM, RAM, and so on during the normal operation mode. In such a microcontroller, an entry into a test mode allows the circuit inside the chip for controlling test operations to operate, and allows the signals transmitted between the internal modules to be transmitted to the exterior from the external terminals of the chip.
FIG. 1 is a drawing showing a mechanism for indicating an entry into a test mode in a semiconductor device having a related-art test mode. A semiconductor device 10 shown in FIG. 1 includes a power supply terminal 11, a power supply terminal 12, a test-purpose signal terminal 13, user terminals 14 through 17, and a power supply terminal 18. The power supply terminals 11 and 12 serve to supply power supply voltages VDD and AVDD, respectively, to the core circuit of the semiconductor device 10. The ground terminal 18 serve to set a ground voltage VSS of the core circuit of the semiconductor device 10 to the same potential as the ground voltage of the external circuit. The user terminals 14 through 17 serve to input/output control signals, data signals, etc., with respect to the core circuit of the semiconductor device 10.
The test-purpose signal terminal 13 is configured to receive a test signal indicative of an entry into a test mode. When the test signal applied from the exterior to the test-purpose signal terminal 13 is set to HIGH, for example, the semiconductor device 10 enters the test mode, thereby performing test operations.
Such a test-purpose signal terminal is only used during the test performed prior to the shipment from the factory by the manufacture of the semiconductor device. After the shipment of the semiconductor device, no user uses this terminal. Namely, the test-purpose signal terminal is a terminal of no use for users.
In respect of a semiconductor device chip, generally, as an attempt is made to increase the number of functions incorporated in the chip, the number of necessary input/output signals increases, resulting in an increase in the number of terminals. Further, as the chip size decreases in response to an increase in the circuit density of a semiconductor device, the size and pitches of the terminals need to be reduced in proportion to the reduction of the chip size. Accordingly, as the function of the semiconductor device becomes sophisticated, and as the circuit density increases, space for arranging the terminals decreases. This results in an increase in the demand that unnecessary terminals should be removed as many as possible.
Moreover, it is desirable to hide the method of entering a test mode from general users, thereby preventing the users having purchased the semiconductor device from using the test mode unpurposely. Further, it is preferable that there is some devised mechanism that avoids an inadvertent entry into a test mode so as to prevent the semiconductor device from entering the test mode by accident.
Patent Document 1 discloses a semiconductor integrated circuit having two power supply systems, which includes a first power supply for use in the core circuit and input buffers and a second power supply for use in the output buffers. After the power-on of the first power supply, a predetermined sequence is given to the second power supply, thereby entering a test mode. Patent Document 2 discloses a semiconductor integrated circuit which enters a test mode based on the result of comparison, which is made between the voltage applied from the exterior to an output terminal electrically coupled to an output of the output driver circuit and either one of the higher power supply voltage or the lower power supply voltage. Patent Document 3 discloses a configuration that generates a test signal for setting the test mode in response to the detection of a specific waveform inside the integrated circuit where a power supply voltage waveform applied in the test mode is controlled.
[Patent Document 1] Japanese Patent Application Publication No. 9-105771
[Patent Document 2] Japanese Patent Application Publication No. 2001-53232
[Patent Document 3] Japanese Patent Application Publication No. 6-309475
Accordingly, there is a need for a semiconductor device that can enter a test mode without requiring the use of an unnecessary terminal.